1. Technical Field of the Invention
The present invention relates to computer systems and, more particularly, to a computer memory system including a memory attribute palette to specify memory attributes for sections of memory.
2. Description of Prior Art
The Pentium.RTM. Pro processor manufactured by Intel Corporation includes two interacting mechanisms that are used together to set the effective memory type of particular sections of memory. The memory type range registers (MTRRs) define the memory attributes for physical address ranges. The page tables allow for memory attributes to be assigned dynamically to linearly addressed pages of memory. The MTRRs are adequate for describing static physical ranges with specific alignment and length constraints that are usually setup by the BIOS, but are incapable of describing the dynamic linearly addressed data structures of programs. The page tables allow for memory attributes to be assigned dynamically to linearly addressed pages of memory. This gives the operating system (OS) and applications flexibility in applying memory attributes to any data structure.
The page tables in the Pentium.RTM. Pro processor offer only a subset of all memory attributes including write through (WT), and uncacheable (UC). The page directory and page table entries include two bits, page cache disable (PCD) and page write-through (PWT), to select memory types. While the remaining two memory types could be specified by using the only remaining reserved bit, doing so would prevent introduction of new memory attributes in the future.
Accordingly, there is a need for a means for providing page table memory type encodings to linear memory ranges in a flexible and expandable manner.